ARM

Exception vectors:

Reset - 0x00

Undefined instruction - 0x04

Software interrupt - 0x08

Prefetch Abort - 0x0c

Data Abort - 0x10

Reserved - 0x14

IRQ - 0x18

FIQ - 0x1c

SPSR

-- to store the current value of the CPSR when an exception is taken so that it can be restored after handling the exception.

- Each exception handling mode can access its own SPSR.

- User mode and System mode do not have an SPSR because they are not exception handling modes.

CPSR holds:

- the APSR flags

- the current processor mode

- interrupt disable flags

- current processor state (ARM, Thumb, ThumbEE, or Jazelle®)

- endianness state (on ARMv4T and later)

- execution state bits for the IT block (on ARMv6T2 and later).

TLB structure

- used for both data accesses and instruction fetches.

-- two parts:

-- an eight-entry fully-associative part used exclusively for holding lockdown TLB entries

-- a set-associative part for all other entries, 2 way x 32 entry.

- which part an instruction is determined by state of the TLB lockdown register

- micro TLB of 32 entries - implemented on each of the instruction and data sides.

The main TLB is the second layer in the TLB structure that catches the misses from the Micro TLBs.

Each TLB entry contains a virtual address, a page size, a physical address, and a set of memory properties.

* Block sizes:

- Supersections - Describe 16MB blocks of memory.

- Sections 1MB

- Large pages - 64KB

- Small pages -4KB

* Supersections, sections and large pages are supported to permit mapping of a large region of memory while using only a single entry in a TLB.

* If no mapping for an address is found within the TLB, then the translation table is automatically read by hardware and a mapping is placed in the TLB.