arm core

ARM Core

- The ARM1136JF-S processor is built around the ARM11 core in an ARMv6 implementation that runs the 32-bit ARM, 16-bit Thumb, and 8-bit Jazelle instruction sets.

- The processor contains EmbeddedICE-RT logic and a JTAG debug interface to enable hardware debuggers to communicate with the processor.

- The core is described in more detail in the following sections:

Instruction set categories

The instruction sets are divided into four categories:

• data processing instructions
• load and store instructions
• branch instructions
• coprocessor instructions.

Note

Only load, store, and swap instructions can access data from memory.

Conditional execution

All ARM instructions are conditionally executed and can optionally update the four condition code flags, Negative, Zero, Carry, and Overflow, according to their result.

Registers

The ARM1136JF-S core contains:

• 31 general-purpose 32-bit registers
• seven dedicated 32-bit registers.

Note

At any one time, 16 registers are visible. The remainder are banked registers used to speed up exception processing.

Modes and exceptions

- seven operating modes, five of which are exception modes:

• User mode
• Supervisor mode

- Exception

• fast interrupt
• normal interrupt
• memory aborts
• software interrupts
• Undefined instruction.

Thumb instruction set

Thumb is an extension to the ARM architecture. It contains a subset of the most commonly-used 32-bit ARM instructions that has been encoded into 16-bit wide opcodes, to reduce memory requirements.

DSP instructions

The ARM DSP instruction set extensions provide the following:

• 16-bit data operations
• saturating arithmetic
• MAC operations.

Multiply instructions are processed using a single-cycle 32x16 implementation. There are 32x32, 32x16, and 16x16 multiply instructions (MAC).

Media extensions

The ARMv6 instruction set provides media instructions to complement the DSP instructions. The media instructions are divided into the following main groups:

• Additional multiplication instructions for handling 16-bit and 32-bit data, including dual-multiplication instructions that operate on both 16-bit halves of their source registers.
• This group includes an instruction that improves the performance and size of code for multiword unsigned multiplications.
• Instructions to perform Single Instruction Multiple Data (SIMD) operations on pairs of 16-bit values held in a single register, or on quadruplets of 8-bit values held in a single register. The main operations supplied are addition and subtraction, selection, pack, and saturation.
• Instructions to extract bytes and halfwords from registers and zero-extend or sign-extend them. These include a parallel extraction of two bytes followed by extension of each byte to a halfword.
• Instructions to perform the unsigned Sum-of-Absolute-Differences (SAD) operation. This is used in MPEG motion estimation.

Datapath

The datapath consists of three pipelines:

• ALU/shift pipe - executes most of the ALU operations, and includes a 32-bit barrel shifter. Three pipeline stages:

- Shift - full barrel shifter. All shifts, including those required by the LSU, are performed

- The saturating left shift, which doubles the value of an operand and saturates it, is implemented in the Shift stage.